The present invention relates to semiconductor devices and the fabrication thereof and, more particularly, to a device with reduced degradation resulting from the formation of bitline contacts.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell has its stacked gate terminal connected to a different word line, while all the flash cells in the array have their source terminals connected to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such single bit stacked gate flash memory cells are programmed by applying a voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide causes a phenomenon called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erase, and application of supplemental erase pulses to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have become much more prevalent. The dual bit memory cells are capable of storing two bits of information in a single memory cell. Recently, dual bit flash memory structures have been introduced that do not utilize a floating gate, such as an charge-trapping flash memory device that employs a polysilicon layer over the charge-trapping dielectric material layer for providing wordline connections. Conventional techniques do not address the characteristics associated with these types of devices.
When charge-trapping memory cells are utilized in a memory array, a charge-trapping dielectric material is formed over the substrate and a plurality of bitlines are formed in the substrate. Between the bitlines and above the charge-trapping dielectric material are formed a plurality of wordlines, generally polysilicon. When the cell is functioning properly, charges are trapped in the charge-trapping dielectric material. However, when contact holes are formed in the bitlines by contact edge tools, plasma charging can damage the dielectric charge-trapping material near the contact holes. Such damage might include the creation of charge trapping areas where none are intended. Consequently, the charge-trapping dielectric material near the contact holes may not trap charges in the same manner as dielectric material farther from the contact holes.
Therefore, there is an unmet need in the art for new and improved memory arrays which employ charge-trapping memory cells and are resistant to degradation resulting from contact hole formation.
According to the present invention, there is provided a memory array comprising a substrate and a plurality of bitlines having contacts. Between the bitlines are a plurality of charge-trapping memory cells with charge-trapping dielectric material formed over the substrate. A plurality of wordlines are formed over the charge-trapping dielectric material. Nitride spacers are formed between the bitline contacts and the wordlines adjacent to the bitline contacts.
Also according to the present invention, there is provided a method for forming a memory array. According to the method, a substrate is provided and a charge-trapping dielectric material is formed over the substrate. A plurality of bitlines having contact locations are formed and wordlines are formed over the charge-trapping dielectric material. Protective spacers are then formed between the bitline contacts locations and the wordlines adjacent to the bitline contact locations. The bitline contacts are then formed at the bitline contact locations.